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4-/6-channel digital potentiometers ad5204/ad5206 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1999C2010 analog devices, inc. all rights reserved. features 256 positions multiple independently programmable channels ad52044-channel ad52066-channel potentiometer replacement terminal resistance of 10 k, 50 k, 100 k 3-wire spi-compatible serial data input +2.7 v to +5.5 v single-supply operation; 2.7 v dual-supply operation power-on midscale preset applications mechanical potentiometer replacement instrumentation: gain, offset adjustment programmable voltage-to-current conversion programmable filters, delays, time constants line impedance matching general description the ad5204/ad5206 provide 4-/6-channel, 256-position digitally controlled variable resistor (vr) devices. these devices perform the same electronic adjustment function as a potentiometer or variable resistor. each channel of the ad5204/ ad5206 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the spi-compatible serial-input register. the resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the vr latch. the variable resistor offers a completely programmable value of resistance between the a terminal and the wiper or the b terminal and the wiper. the fixed a-to-b terminal resistance of 10 k, 50 k, or 100 k has a nominal temperature coefficient of 700 ppm/c. each vr has its own vr latch that holds its programmed resistance value. these vr latches are updated from an internal serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. eleven data bits make up the data-word clocked into the serial input register. the first three bits are decoded to determine which vr latch is loaded with the last eight bits of the data-word when the cs strobe is returned to logic high. a serial data output pin at the opposite end of the serial register (ad5204 only) allows simple daisy chaining in multiple vr applications without requiring additional external decoding logic. functional block diagrams d7 d0 a1 w1 b1 v dd ad5204 cs clk 8 en addr dec a2 a1 a0 sdi di ser reg d0 d7 a4 w4 b4 gnd rdac latch 1 r d7 d0 rdac latch 4 r power-on preset v ss sdo do pr shdn 0 6884-001 figure 1. d7 d0 a1 w1 b1 v dd ad5206 cs clk 8 en addr dec a2 a1 a0 sdi di ser reg d0 d7 a6 w6 b6 gnd r d7 d0 rdac latch 6 rdac latch 1 r v ss power-on preset 06884-002 figure 2. an optional reset ( pr ) pin forces all the ad5204 wipers to the midscale position by loading 0x80 into the vr latch. the ad5204/ad5206 are available in the 24-lead surface- mount soic, tssop, and pdip packages. the ad5204 is also available in a 32-lead, 5 mm 5 mm lfcsp package. all parts are guaranteed to operate over the extended industrial temperature range of ?40c to +85c. for additional single-, dual-, and quad- channel devices, see the ad8400 / ad8402 / ad8403 data sheets.
ad5204/ad5206 rev. c | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagrams............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical characteristics............................................................. 3 timing diagrams.............................................................................. 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ........................................... 10 operation......................................................................................... 12 programming the variable resistor............................................. 13 rheostat operation .................................................................... 13 programming the potentiometer divider ................................... 14 voltage output operation......................................................... 14 digital interfacing .......................................................................... 15 test circuits..................................................................................... 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 18 revision history 7/10rev. b to rev. c changes to digital input and output voltage to gnd parameter, table 2............................................................................. 6 changes to ordering guide .......................................................... 18 5/09rev. a to rev. b changes to table 1............................................................................ 3 changes to absolute maximum ratings ....................................... 6 changes to figure 7.......................................................................... 8 changes to table 4............................................................................ 8 11/07rev. 0 to rev. a updated format..................................................................universal added 32-lead lfcsp package .......................................universal changed r ba to r ab ............................................................universal changes to absolute maximum ratings........................................6 changes to operation section...................................................... 12 updated outline dimensions....................................................... 17 changes to ordering guide .......................................................... 18 9/99revision 0: initial version
ad5204/ad5206 rev. c | page 3 of 20 specifications electrical characteristics v dd = 5 v 10% or 3 v 10%, v ss = 0 v, v a = v dd , v b = 0 v, ?40c < t a < +85c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode 2 resistor differential nl 3 r-dnl r wb , v a = no connect ?1 0.25 +1 lsb resistor nonlinearity error 3 r-inl r wb , v a = no connect ?2 0.5 +2 lsb nominal resistor tolerance 4 r ab t a = 25c ?30 +30 % resistance temperature coefficient r ab /t v ab = v dd , wiper = no connect 700 ppm/c nominal resistance match r/r ab channel 1 to channel 2, channel 3, and channel 4, or to channel 5 and channel 6; v ab = v dd 0.25 1.5 % wiper resistance r w i w = 1 v/r, v dd = 5 v 50 100 dc characteristics potentiometer divider mode 2 resolution n 8 bits differential nonlinearity 5 dnl ?1 0.25 +1 lsb integral nonlinearity 5 inl ?2 0.5 +2 lsb voltage divider temperature coefficient v w /t code = 0x40 15 ppm/c full-scale error v wfse code = 0x7f ?2 ?1 0 lsb zero-scale error v wzse code = 0x00 0 1 2 lsb resistor terminals voltage range 6 v a , v b , v w v ss v dd v capacitance 7 ax, bx c a , c b f = 1 mhz, measured to gnd, code = 0x40 45 pf capacitance 7 wx c w f = 1 mhz, measured to gnd, code = 0x40 60 pf shutdown current 8 i a_sd 0.01 5 a common-mode leakage i cm v a = v b = v w = 0, v dd = +2.7 v, v ss = ?2.5 v 1 na digital inputs and outputs input logic high v ih v dd = 5 v/3 v 2.4/2.1 v input logic low v il v dd = 5 v/3 v 0.8/0.6 v output logic high v oh r pullCup = 1 k to 5 v 4.9 v output logic low v ol i ol = 1.6 ma, v logic = 5 v 0.4 v input current i il v in = 0 v or 5 v 1 a input capacitance 7 c il 5 pf power supplies power single-supply range v dd range v ss = 0 v 2.7 5.5 v power dual-supply range v dd /v ss range 2.3 2.7 v positive supply current i dd v ih = 5 v or v il = 0 v 12 60 a negative supply current i ss v ss = ?2.5 v, v dd = +2.7 v 12 60 a power dissipation 9 p diss v ih = 5 v or v il = 0 v 0.3 mw power supply sensitivity pss v dd = 5 v 10% 0.0002 0.005 %/% dynamic characteristics 7 , 10 bandwidth ?3 db bw_10k r ab = 10 k 721 khz bw_50k r ab = 50 k 137 khz bw_100k r ab = 100 k 69 khz total harmonic distortion thd w v a = 1.414 v rms, v b = 0 v dc, f = 1 khz 0.004 % vw settling time (10 k/50 k/100 k) t s v a = 5 v, v b = 0 v, 1 lsb error band 2/9/18 s resistor noise voltage e n_wb r wb = 5 k, f = 1 khz, pr = 0 9 nv/hz
ad5204/ad5206 rev. c | page 4 of 20 parameter symbol conditions min typ 1 max unit interface timing characteristics 7 , 11 , 12 input clock pulse width t ch , t cl clock level high or low 20 ns data setup time t ds 5 ns data hold time t dh 5 ns clk-to-sdo propagation delay 13 t pd r l = 2 k , c l < 20 pf 1 150 ns cs setup time t css 15 ns cs high pulse width t csw 40 ns reset pulse width t rs 90 ns clk fall to cs fall setup t csh0 0 ns clk fall to cs rise hold time t csh1 0 ns cs rise to clock rise setup t cs1 10 ns 1 typicals represent averag e readings at 25c and v dd = 5 v. 2 applies to all vrs. 3 resistor position nonlinearity error (r-inl) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from the ideal position between successive tap positions. parts are guaranteed monotoni c. see the test circuit in figure 28. i w = v dd /r for both v dd = 3 v and v dd = 5 v. 4 v ab = v dd , wiper (v w ) = no connect. 5 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic at operat ing conditions. see the test circuit in figure 27. 6 resistor terminal a, ter minal b, and wiper w have no limitations on polarity with respect to each other. 7 guaranteed by design and not subject to production test. 8 measured at the ax terminals. all ax terminals are open circuited in shutdown mode. 9 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = 5 v. 11 applies to all parts. 12 see the timing diagrams (figure 3 to figure 5) for the location of the measured valu es. all input control voltages are specifi ed with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. swit ching characteristics ar e measured using both v dd = 3 v and v dd = 5 v. 13 the propagation delay depends on the values of v dd , r l , and c l (see the operation section).
ad5204/ad5206 rev. c | page 5 of 20 timing diagrams 06884-003 sdi clk v out cs 1 0 1 0 1 0 v dd 0v a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 rdac latch load figure 3. timing diagram sdi (data in) sdo (data out) 1 0 1 0 1 0 1 0 v dd 0v clk cs v out ax or dx ax or dx ax or dx ax or dx t css t dh t pd_max t csh0 1 lsb error band 1 lsb t csh1 t ch t csw t s t cl t ds t cs1 06884-004 figure 4. detailed timing diagram 1 lsb 1 lsb error band 1 0 v dd 0v v out t rs t s pr 0 6884-005 figure 5. ad5204 preset timing diagram
ad5204/ad5206 rev. c | page 6 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. parameter rating v dd to gnd ?0.3 v to +7 v v ss to gnd 0 v to ?7 v v dd to v ss 7 v v a , v b , v w to gnd v ss , v dd i a , i b , i w pulsed 1 20 ma continuous 10 k end-to-end resistance 11 ma 50 k and 100 k end-to-end resistance 2.5 ma digital input and output voltage to gnd ?0.3 v to (v dd + 0.3 v) or 7 v (whichever is less) operating temperature range ?40c to +85c maximum junction temperature (t j max) 150c storage temperature ?65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec package power dissipation (t j max ? t a )/ ja thermal resistance, ja 2 pdip (n-24-1) 63c/w soic (rw-24) 52c/w tssop (ru-24) 50c/w lfcsp (cp-32-3) 32.5c/w esd caution 1 maximum terminal current is bounde d by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 thermal resistance (jedec 4-layer (2s2p) board). paddle soldered to board.
ad5204/ad5206 rev. c | page 7 of 20 pin configurations and function descriptions nc 1 nc 2 gnd 3 cs 4 b4 24 w4 23 a4 22 b2 21 pr 5 v dd 6 shdn 7 w2 20 a2 19 a1 18 sdi 8 w1 17 clk 9 b1 16 sdo 10 a3 15 v ss 11 w3 14 nc 12 b3 13 ad5204 top view (not to scale) nc = no connect 06884-006 figure 6. ad5204 soic/tssop/pdip pin configuration table 3. ad5204 soic/tssop/pdip pin function descriptions pin no. name description 1, 2, 12 nc not connected. 3 gnd ground. 4 cs chip select input (active low). when cs returns high, data in the serial input register is decoded based on the address bits, and then it is loaded into the target rdac latch. 5 pr preset to midscale (active low). this pin sets the rdac registers to 0x80. 6 v dd positive power supply. this pin is specified for operation at both 3 v and 5 v. it is the sum of |v dd | + |v ss | < 5.5 v. 7 shdn terminal a open-circuit shutdown (active low input). this pin controls vr 1 through vr 4. 8 sdi serial data input. data is input msb first. 9 clk serial clock input. this pin is positive edge triggered. 10 sdo serial data output. this pin is an open- drain transistor and requires a pull-up resistor. 11 v ss negative power supply. this pin is specified for operation at both 0 v and ?2.7 v. it is the sum of |v dd | + |v ss | < 5.5 v. 13 b3 terminal b rdac 3. 14 w3 wiper rdac 3. address = 010 2 . 15 a3 terminal a rdac 3. 16 b1 terminal b rdac 1. 17 w1 wiper rdac 1. address = 000 2 . 18 a1 terminal a rdac 1. 19 a2 terminal a rdac 2. 20 w2 wiper rdac 2. address = 001 2 . 21 b2 terminal b rdac 2. 22 a4 terminal a rdac 4. 23 w4 wiper rdac 4. address = 011 2 . 24 b4 terminal b rdac 4.
ad5204/ad5206 rev. c | page 8 of 20 nc nc nc nc b3 a3 w3 nc nc nc nc b4 w4 a4 nc notes 1. nc = no connect. 2. the lfcsp package has an exposed paddle that should be connected to gnd and the associated pcb ground plate. nc b1 w1 a1 a2 w2 nc b2 sdo clk sdi shdn pr cs gnd 1 2 3 4 5 6 7 8 23 22 21 18 19 20 24 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ad5204 top view (not to scale) v dd v s s 06884-053 pin 1 indicator figure 7. ad5204 lfcsp pin configuration table 4. ad5204 lfcsp pin function descriptions pin no. name description 1 v ss negative power supply. this pin is specified for operation at both 0 v and ?2.7 v. it is the sum of |v dd | + |v ss | < 5.5 v. 2 to 5, 9, 16, 17, 21 to 24 nc not connected. 6 b3 terminal b rdac 3. 7 w3 wiper rdac 3. address = 010 2 . 8 a3 terminal a rdac 3. 10 b1 terminal b rdac 1. 11 w1 wiper rdac 1. address = 000 2 . 12 a1 terminal a rdac 1. 13 a2 terminal a rdac 2. 14 w2 wiper rdac 2. address = 001 2 . 15 b2 terminal b rdac 2. 18 a4 terminal a rdac 4. 19 w4 wiper rdac 4. address = 011 2 . 20 b4 terminal b rdac 4. 25 gnd ground. 26 cs chip select input (active low). when cs returns high, data in the serial input register is decoded based on the address bits, and then it is loaded into the target rdac latch. 27 pr preset to midscale (active low). this pin sets the rdac registers to 0x80. 28 v dd positive power supply. this pin is specified for operation at both 3 v and 5 v. it is the sum of |v dd | + |v ss | < 5.5 v. 29 shdn terminal a open-circuit shutdown (active low input). this pin controls vr 1 through vr 4. 30 sdi serial data input. data is input msb first. 31 clk serial clock input. this pin is positive edge triggered. 32 sdo serial data output. this pin is an open- drain transistor and requires a pull-up resistor.
ad5204/ad5206 rev. c | page 9 of 20 a6 1 w6 2 b6 3 gnd 4 b4 24 w4 23 a4 22 b2 21 cs 5 v dd 6 sdi 7 w2 20 a2 19 a1 18 clk 8 w1 17 v ss 9 b1 16 b5 10 a3 15 w5 11 w3 14 a5 12 b3 13 ad5206 top view (not to scale) nc = no connect 06884-019 figure 8. ad5206 soic/tssop/pdip pin configuration table 5. ad5206 pin function descriptions pin no. name description 1 a6 terminal a rdac 6. 2 w6 wiper rdac 6. address = 101 2 . 3 b6 terminal b rdac 6. 4 gnd ground. 5 cs chip select input (active low). when cs returns high, data in the serial in put register is decoded based on the address bits, and then it is loaded into the target rdac latch. 6 v dd positive power supply. this pin is specified for operation at both 3 v and 5 v. it is the sum of |v dd | + |v ss | < 5.5 v. 7 sdi serial data input. data is input msb first. 8 clk serial clock input. this pin is positive edge triggered. 9 v ss negative power supply. this pin is specified for operation at both 0 v and ?2.7 v. it is the sum of |v dd | + |v ss | < 5.5 v. 10 b5 terminal b rdac 5. 11 w5 wiper rdac 5. address = 100 2 . 12 a5 terminal a rdac 5. 13 b3 terminal b rdac 3. 14 w3 wiper rdac 3. address = 010 2 . 15 a3 terminal a rdac 3. 16 b1 terminal b rdac 1. 17 w1 wiper rdac 1. address = 000 2 . 18 a1 terminal a rdac 1. 19 a2 terminal a rdac 2. 20 w2 wiper rdac 2. address = 001 2 . 21 b2 terminal b rdac 2. 22 a4 terminal a rdac 4. 23 w4 wiper rdac 4. address = 011 2 . 24 b4 terminal b rdac 4.
ad5204/ad5206 rev. c | page 10 of 20 typical performance characteristics 120 110 30 70 60 50 40 90 80 100 v dd /v ss = 2.7v ?3.0 ?2.0 ?1.0 0 1.0 2.0 3.0 4.0 5.0 6.0 switch resistance ( ? ) common mode (v) v dd /v ss = 5.5v/0v v dd /v ss = 2.7v/0v 06884-007 ?4 ?2 0 50k ? 100k ? 10k? v dd = 2.7v v ss = ?2.7v v a = 100mv rms data = 0x 80 1k 10k 100k 1m normalized gain (db) frequency (hz) op42 v a 06884-010 figure 9. incremental on resistance of the wiper vs. voltage figure 12. ?3 db bandwidth vs. terminal resistance, 2.7 v dual-supply operation 100 1k 10k 100k gain (db) frequency (hz) 50k ? 100k ? 10k? v a op42 v b = 0v v dd = +2.7v v ss = ?2.7v v a = 100mv rms data = 0x80 t a = 25c ? 5.99 ?6.09 ?6.08 ?6.07 ?6.06 ?6.05 ?6.04 ?6.03 ?6.02 ?6.01 ?6.00 0 6884-008 1k 10k 100k 1m gain (db) frequency (hz) 0 ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 data = 0x80 data = 0x40 data = 0x20 data = 0x10 data = 0x08 data = 0x04 data = 0x02 data = 0x01 v dd = +2.7v v ss = ?2.7v v a = 100mv rms t a = 25c v a op42 06884-011 figure 10. gain flatness vs. frequency figure 13. bandwidth vs. code, 10 k version 1k 10k 100k 1m gain (db) frequency (hz) 0 ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 data = 0x80 data = 0x40 data = 0x20 data = 0x10 data = 0x08 data = 0x04 data = 0x02 data = 0x01 v dd = +2.7v v ss = ?2.7v v a = 100mv rms t a = 25c v a op42 06884-012 ?4 ?2 0 50k ? 100k ? 10k? 1k 10k 100k 1m normalized gain (db) frequency (hz) op42 +1.5v 2.7v v dd = 2.7v v ss = 0v v a = 100mv rms data = 0x80 t a = 25c 0 6884-009 figure 11. ?3 db bandwidth vs. terminal resistance, 2.7 v single-supply operation figure 14. bandwidth vs. code, 50 k version
ad5204/ad5206 rev. c | page 11 of 20 1k 10k 100k 1m gain (db) frequency (hz) 0 ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 data = 0x80 data = 0x40 data = 0x20 data = 0x10 data = 0x08 data = 0x04 data = 0x02 data = 0x01 v dd = +2.7v v ss = ?2.7v v a = 100mv rms t a = 25c v a op42 06884-013 figure 15. bandwidth vs. code, 100 k version 123456 trip point (v) supply voltage v dd (v) dual supply v ss = 0v single supply v dd = v ss 2.5 2.0 0 1.5 1.0 0.5 06884-014 figure 16. digital input trip point vs. supply voltage 100 0.001 0.01 0.1 1 10 0123456 supply current (ma) incremental input logic voltage (v) i ss at v dd /v ss = 2.7v t a = 25c i dd at v dd /v ss = 2.7v i dd at v dd /v ss = 2.7v/0v i dd at v dd /v ss = 5.5v/0v 06884-015 figure 17. supply current vs. input logic voltage 8 7 6 5 4 3 2 1 0 10k 100k 1m 10m supply current (ma) frequency (hz) i dd , v dd /v ss = 5.5v/0v, data = 0x 55 i ss , v dd /v ss = 2.7v, data = 0x 55 i ss , v dd /v ss = 2.7v, data = 0x ff i dd , v dd /v ss = 5v/0v, data = 0x ff i dd , v dd /v ss = 2.7v/0v, data = 0x ff i dd , v dd /v ss = 2.7v/0v, data = 0x 55 t a = 25c 06884-016 figure 18. supply current vs. clock frequency 60 0 10 20 30 40 50 10 100 1k 10k 100k psrr (db) frequency (hz) t a = 25c v dd = 5.0v 10% v dd = 3.0v 10% v ss = ?3.0v 10% 06884-017 figure 19. power supply re jection vs. frequency 1 v dd = +2.7v v ss = ?2.7v t a = 25c r ab = 10k ? noninverting test circuit inverting test circuit 0.0001 0.001 0.01 0.1 10 100 1k 10k 100k thd + noise (%) frequency (hz) 0 6884-018 figure 20. total harmonic distortion plus noise vs. frequency
ad5204/ad5206 rev. c | page 12 of 20 operation the ad5204 provides a 4-channel, 256-position digitally controlled vr device, and the ad5206 provides a 6-channel, 256-position digitally controlled vr device. changing the pro- grammed vr settings is accomplished by clocking an 11-bit serial data-word into the sdi pin. the format of this data-word is three address bits, msb first, followed by eight data bits, msb first. table 6 provides the serial register data-word format. table 6. serial data-word format address data b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb msb lsb 2 10 2 8 2 7 2 0 see table 10 for the ad5204/ad5206 address assignments to decode the location of the vr latch receiving the serial register data in bit b7 through bit b0. the vr outputs can be changed one at a time in random sequence. the ad5204 presets to midscale by asserting the pr pin, simplifying fault condition recovery at power up. both parts have an internal power-on preset that places the wiper in a preset midscale condition at power on. in addition, the ad5204 contains a power shutdown pin ( shdn ) that places the rdac in a zero power consumption state, where terminals ax are open circuited and wipers wx are connected to terminals bx, resulting in only leakage currents being consumed in the vr structure. in shutdown mode, the vr latch settings are maintained so that the vr settings return to their previous resistance values when the device is returned to operational mode from power shutdown. d7 d6 d5 d4 d3 d2 d1 d0 rdac latch and decoder ax wx bx r s s hdn r s r s r s 06884-044 figure 21. ad5204/ad5206 equivalent rdac circuit
ad5204/ad5206 rev. c | page 13 of 20 programming the variable resistor rheostat operation the nominal resistance of the rdac between terminal a and terminal b is available with values of 10 k, 50 k, and 100 k. the last digits of the part number determine the nominal resistance value; for example, 10 k = 10 and 100 k = 100. the nominal resistance (r ab ) of the vr has 256 contact points accessed by the wiper terminal, plus terminal b contact. the 8-bit data-word in the rdac latch is decoded to select one of the 256 possible settings. the first connection of the wiper starts at terminal b for the 0x00 data. this terminal b connection has a wiper contact resistance of 45 . the second connection (for a 10 k part) is the first tap point, located at 84 [= r ab (nominal resistance)/256 + r w = 84 + 45 ] for the 0x01 data. the third connection is the next tap point, representing 78 + 45 = 123 for the 0x02 data. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,006 . the wiper does not directly connect to terminal a. see figure 21 for a simplified diagram of the equivalent rdac circuit. the general transfer equation determining the digitally programmed output resistance between the wx and bx terminals is r wb ( dx ) = (dx )/256 r ab + r w (1) where dx is the data contained in the 8-bit rdacx latch, and r ab is the nominal end-to-end resistance. for example, when v b = 0 v and terminal a is open circuited, the output resistance values are set as outlined in table 7 for the rdac latch codes (applies to the 10 k potentiometer). table 7. output resistance va lues for the rdac latch codes v b = 0 v and terminal a = open circuited d (dec) r wb () output state 255 10006 full scale 128 5045 midscale ( pr = 0 condition) 1 84 1 lsb 0 45 zero scale (wiper contact resistance) in the zero-scale condition, a finite total wiper resistance of 45 is present. regardless of which setting the part is operating in, care should be taken to limit the current between terminal a to ter mina l b, wip er w to ter m i na l a, and wip er w to ter min a l b, to the maximum continuous current of 5.65 ma(10 k) or 1.35 ma(50 k and 100 k) or pulse current of 20 ma. otherwise, degradation or possible destruction of the internal switch contact, can occur. like the mechanical potentiometer that the rdac replaces, the rdac is completely symmetrical. the resistance between wiper w and terminal a produces a digitally controlled resistance, r wa . when these terminals are used, terminal b should be tied to the wiper. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded to the latch is increased in value. the general transfer equation for this operation is r wa ( dx ) = (256 ? dx )/256 r ab + r w (2) where dx is the data contained in the 8-bit rdacx latch, and r ab is the nominal end-to-end resistance. for example, when v a = 0 v and terminal b is tied to wiper w, the output resistance values outlined in table 8 are set for the rdac latch codes. table 8. output resistance values for the rdac latch codes v a = 0 v and terminal b tied to wiper w d (dec) r wa () output state 255 84 full scale 128 5045 midscale ( pr = 0 condition) 1 10006 1 lsb 0 10045 zero scale the typical distribution of r ab from channel to channel matches to within 1%. however, device-to-device matching is process lot dependent, having a 30% variation. the change in r ab in terms of temperature has a 700 ppm/c temperature coefficient.
ad5204/ad5206 rev. c | page 14 of 20 programming the potentiometer divider voltage output operation the digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. for example, connecting terminal a to 5 v and terminal b to ground produces an output voltage at the wiper that can be any value from 0 v up to 1 lsb less than +5 v. each lsb of voltage is equal to the voltage applied across terminal a and terminal b divided by the 256-position resolution of the potentiometer divider. the general equation defining the output voltage with respect to ground for any given input voltage applied to terminal a and terminal b is v w ( dx ) = dx /256 v ab + v b (3) operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. in this mode, the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the drift improves to 15 ppm/c. pr a1 w1 b1 v dd cs clk sdo* d7 d0 rdac latch 4/6 r a4/a6 w4/w6 b4/b6 d7 d0 en addr dec a1 a2 a0 d7 sdi do di ser reg d0 shdn* dgnd 8 *ad5204 only rdac latch 1 r ad5204/ad5206 06884-047 figure 22. block diagram
ad5204/ad5206 rev. c | page 15 of 20 digital interfacing the ad5204/ad5206 each contain a standard 3-wire serial input control interface. the three inputs are clock (clk), chip select input ( cs ), and serial data input (sdi). the positive- edge-sensitive clk input requires clean transitions to avoid clocking incorrect data into the serial input register. standard logic families work well. if mechanical switches are used for product evaluation, they should be debounced by a flip-flop or by other suitable means. shows more detail of the internal digital circuitry. when figure 22 cs is taken active low, the clock loads data into the serial register on each positive clock edge (see ). when using a positive (v dd ) and negative (v ss ) supply voltage, the logic levels are still referenced to digital ground (gnd). table 9 the serial data output (sdo) pin contains an open-drain n-channel fet. this output requires a pull-up resistor to transfer data to the sdi pin of the next package. the pull-up resistor termination voltage can be larger than the v dd supply of the ad5204. for example, the ad5204 can operate at v dd = 3.3 v, and the pull-up for the interface to the next device can be set at 5 v. this allows for daisy chaining several rdacs from a single-processor serial data line. if a pull-up resistor is used to connect the sdi pin of the next device in the series, the clock period must be increased. capacitive loading at the daisy-chain node (where sdo and sdi are connected) between the devices must be accounted for to successfully transfer data. when daisy chaining is used, the cs should be kept low until all the bits of every package are clocked into their respective serial registers, ensuring that the address bits and data bits are in the proper decoding locations. this requires 22 bits of address and data complying to the data- word format outlined in if two ad5204 4-channel rdacs are daisy-chained. during shutdown ( table 6 shdn ), the sdo output pin is forced to the off (logic high state) position to disable power dissipation in the pull-up resistor. see for the equivalent sdo output circuit schematic. figure 24 table 9. input logic control truth table 1 clk cs pr shdn register activity l l h h no sr effect; enables sdo pin. p l h h shift one bit in from the sdi pin. the 11 th bit entered is shifted out of the sdo pin. x p h h load sr data into the rdac latch based on a2, a1, a0 decode ( table 10 ). x h h h no operation. x x l h sets all rdac latches to midscale; wiper centered and sdo latch cleared. x h p h latches all rdac latches to 0x80. x h h l open circuits all a resistor terminals, connects wiper w to terminal b, and turns off the sdo output transistor. 1 p = positive edge, x = dont care, sr = shift register. table 10. address decode table a2 a1 a0 latch decoded 0 0 0 rdac 1 0 0 1 rdac 2 0 1 0 rdac 3 0 1 1 rdac 4 1 0 0 rdac 5 ad5206 only 1 0 1 rdac 6 ad5206 only the data setup and data hold times in the specification table determine the data valid time requirements. the last 11 bits of the data-word entered into the serial register are held when cs returns high. when cs goes high, the address decoder is gated, enabling one of four or six positive-edge-triggered rdac latches (see for details). figure 23 addr decode rdac 1 rdac 2 rdac 4/ rdac 6 serial register a d5204/ad5206 sdi clk cs 06884-048 figure 23. equivalent input control logic the target rdac latch is loaded with the last eight bits of the serial data-word, completing one dac update. four separate 8-bit data-words must be clocked in to change all four vr settings. serial register sdi ck rs d shdn cs clk pr sdo gnd q 06884-049 figure 24. detail sdo output schematic of the ad5204 all digital pins ( cs , sdi, sdo, pr , shdn , and clk) are protected with a series input resistor and a parallel zener esd structure (see ). figure 25
ad5204/ad5206 rev. c | page 16 of 20 test circuits 340k ? v ss logic 06884-050 figure 25. esd protection of digital pins a, b, w 06884-051 v ss figure 26. esd protection of resistor terminals v+ dut v ms a b w v+ = v dd 1lsb = v+/256 06884-036 figure 27. potentiometer divider nonlinearity error test circuit (inl, dnl) dut v ms a b w no connect i w 06884-037 figure 28. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) v+ a b w dut i ms v ms i w = 1v/r nominal i w v w v+ v dd r w = where v w1 = v ms when i w = 0 and v w2 = v ms when i w = 1/r v w2 ? [v w1 + i w (r aw ii r bw )] 0 6884-052 figure 29. wiper resistance test circuit v+ a b w ~ v a v ms v dd v+ = v dd 10% psrr (db) = 20 log ? v ms ? v dd pss (%/%) = ? v ms % ? v dd % ( ) 0 6884-039 figure 30. power supply sensitivity test circuit (pss, psrr) a v in offset bias op279 5v v out dut w offset gnd b 0 6884-040 figure 31. inverting programmable gain test circuit a v in offset bias op279 5 v v out dut w offset gnd b 06884-041 figure 32. noninverting programmable gain test circuit b a v in 2.5v +15v v out dut w ?15v o ffset gnd op42 0 6884-042 figure 33. gain vs. frequency test circuit dut i sw b w v ss to v dd r sw = 0.1 v i sw code = 0x00 0.1v + ? 06884-043 figure 34. incremental on-resistance test circuit
ad5204/ad5206 rev. c | page 17 of 20 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001 071006-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 24 1 12 13 0.100 (2.54) bsc 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 35. 24-lead plastic dual in-line package [pdip] narrow body (n-24-1) dimensions shown in inches and (millimeters) compliant to jedec standards ms-013-ad controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. 15.60 (0.6142) 15.20 (0.5984) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 24 13 12 1 1.27 (0.0500) bsc 06-07-2006-a figure 36. 24-lead standard small outline package [soic_w] wide body (rw-24) dimensions shown in millimeters and (inches)
ad5204/ad5206 rev. c | page 18 of 20 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 37. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.45 3.30 sq 3.15 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) 112408-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 38. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-3) dimensions shown in millimeters ordering guide model 1, 2 k temperature range package description package option ad5204bn10 10 ?40c to +85c 24-lead plastic dual in-line package [pdip] n-24-1 ad5204br10 10 ?40c to +85c 24-lead standard small outline package [soic_w] rw-24 ad5204br10-reel 10 ?40c to +85c 24-lead st andard small outline package [soic_w] rw-24 ad5204brz10 10 ?40c to +85c 24-lead standard small outline package [soic_w] rw-24 ad5204brz10-reel 10 ?40c to +85c 24-lead stan dard small outline package [soic_w] rw-24 ad5204bru10 10 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5204bru10-reel7 10 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5204bruz10 10 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 AD5204BRUZ10-REEL7 10 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5204bcpz10-reel 10 ?40c to +85c 32-lead frame chip scale package [lfcsp_vq] cp-32-3 ad5204bcpz10-reel7 10 ?40c to +85c 32-lead frame chip scale package [lfcsp_vq] cp-32-3 ad5204bn50 50 ?40c to +85c 24-lead pl astic dual in-line package [pdip] n-24-1 ad5204br50 50 ?40c to +85c 24-lead standard small outline package [soic_w] rw-24 ad5204br50-reel 50 ?40c to +85c 24-lead st andard small outline package [soic_w] rw-24 ad5204brz50 50 ?40c to +85c 24-lead standard small outline package [soic_w] rw-24
ad5204/ad5206 rev. c | page 19 of 20 model 1, 2 k temperature range package description package option ad5204brz50-reel 50 ?40c to +85c 24-lead st andard small outline package [soic_w] rw-24 ad5204bru50 50 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5204bru50-reel 50 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5204bru50-reel7 50 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5204bruz50 50 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5204bruz50-reel7 50 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5204bn100 100 ?40c to +85c 24-lead pl astic dual in-line package [pdip] n-24-1 ad5204br100 100 ?40c to +85c 24-lead standard small outline package [soic_w] rw-24 ad5204br100-reel 100 ?40c to +85c 24-lead st andard small outline package [soic_w] rw-24 ad5204brz100 100 ?40c to +85c 24-lead standard small outline package [soic_w] rw-24 ad5204brz100-reel 100 ?40c to +85c 24-lead st andard small outline package [soic_w] rw-24 ad5204bru100 100 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5204bru100-reel7 100 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5204bruz100 100 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5204bruz100-r7 100 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5206bn10 10 ?40c to +85c 24-lead pl astic dual in-line package [pdip] n-24-1 ad5206br10 10 ?40c to +85c 24-lead standard small outline package [soic_w] rw-24 ad5206br10-reel 10 ?40c to +85c 24-lead st andard small outline package [soic_w] rw-24 ad5206brz10 10 ?40c to +85c 24-lead standard small outline package [soic_w] rw-24 ad5206brz10-reel 10 ?40c to +85c 24-lead st andard small outline package [soic_w] rw-24 ad5206bru10 10 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5206bru10-reel7 10 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5206bruz10 10 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5206bruz10-rl7 10 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5206bn50 50 ?40c to +85c 24-lead pl astic dual in-line package [pdip] n-24-1 ad5206br50 50 ?40c to +85c 24-lead standard small outline package [soic_w] rw-24 ad5206br50-reel 50 ?40c to +85c 24-lead st andard small outline package [soic_w] rw-24 ad5206brz50 50 ?40c to +85c 24-lead standard small outline package [soic_w] rw-24 ad5206bru50 50 ?40c to +85c 24-lead stan dard small outline package [soic_w] rw-24 ad5206bru50-reel 50 ?40c to +85c 24-lead st andard small outline package [soic_w] rw-24 ad5206bru50-reel7 50 ?40c to +85c 24-lead standard small outline package [soic_w] rw-24 ad5206bruz50 50 ?40c to +85c 24-lead stan dard small outline package [soic_w] rw-24 ad5206bruz50-reel7 50 ?40c to +85c 24-lead st andard small outline package [soic_w] rw-24 ad5206bn100 100 ?40c to +85c 24-lead pl astic dual in-line package [pdip] n-24-1 ad5206br100 100 ?40c to +85c 24-lead standard small outline package [soic_w] rw-24 ad5206br100-reel 100 ?40c to +85c 24-lead st andard small outline package [soic_w] rw-24 ad5206brz100 100 ?40c to +85c 24-lead standard small outline package [soic_w] rw-24 ad5206bru100 100 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5206bru100-reel7 100 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5206bruz100 100 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad5206bruz100-rl7 100 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 1 the ad5204/ad5206 each contains 5,925 transistors. die size is 92 mil 114 mil, or 10,488 sq. mil. 2 z = rohs compliant part.
ad5204/ad5206 rev. c | page 20 of 20 notes ?1999C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06884-0-7/10(c)

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